1. Field of the Invention
The present invention generally relates to a bit synchronizing circuit used in high-speed serial communications and a semiconductor device therewith.
2. Description of the Related Art
As widely known, data are generally transmitted and received by using a reference clock of the same frequency in high-speed serial communications, wherein a transmission speed of a transmission side and a reception speed of a receiving side are mutually predetermined. In order that the receiving side correctly receive the data transmitted from the transmission side, both sides need to operate synchronously. Although there is a method of supplying a clock signal for synchronizing with a data signal to the transmission and receiving sides, there are problems, such as signal wave distortion, reflection, interference in a cable, and interference in a board if the method is applied to recent high-speed serial communications at a clock speed of hundreds of MHz or tens of GHz. For this reason, redundant bits are added to the data signal on the transmission side, encoded such that transition of the data signal is secured at a fixed interval, and transmitted, instead of sending the clock signal used for communications apart from the data signal. On the reception side, since the data sent from the transmission side include timing information, the data are usually sampled, and excessive bits are decoded after the sampling.
For example, in the case of data that are NRZ (non-return to zero) encoded on the transmission side, the receiving side is required to generate a synchronous clock signal for data sampling by using a bit synchronizing circuit such that the data are correctly received. Therefore, a clock of a frequency higher than the transmission speed is supplied to the bit synchronizing circuit, and a circuit is constituted so that the synchronous clock is generated, the clock falling in the center of the data. Recently, the transmission speed of the serial communications interface has become up to hundreds of Mbps to several Gbps, and in order to realize the high-speed and highly reliable communications, the bit synchronizing circuit is required to provide high-performance and high reliability of the communications.
A conventional bit synchronizing circuit 100 used in high-speed serial communications is shown in FIG. 10. A reference clock signal REFCLK and a data input signal SDIN are provided to the bit synchronizing circuit 100. A phase comparison clock generation circuit 110 generates a bit operation clock signal (not shown in FIG. 10) of the frequency corresponding to the transmission speed from the reference clock signal REFCLK, and a total of eight clock signals CLK1-CLK8, each having different phases, are further generated based on the bit operation clock signal.
FIG. 11 is a timing chart of the reference clock signal, the bit operation clock signal, and the clock signals CLK1-CLK8 generated based on the bit operation clock signal. Each of the clock signals CLK1-CLK8 has a phase that is ⅛ cycle shifted in comparison with respective adjacent clock signals. Each of the clock signals CLK1-CLK8 is supplied to an input data edge detection unit 120 and a clock selection unit 140 via a route independent of other clock signals.
The input data edge detection unit 120 detects edge signals EDGE1-EDGE8, as a result of the data input signal SDIN and the clock signals CLK1-CLK8 with different phases being input. The edge signals EDGE1-EDGE8 are supplied to a clock judging (determining) unit 130. In the clock judging unit 130, a clock selection signal CKSL is generated from the edge position recognized based on the edge signals EDGE1-EDGE8. The clock selection signal CKSL and the clock signals CLK1-CLK8 are supplied to the clock selection unit 140.
In the clock selection unit 140, a clock signal for writing WRCK is generated, which is a clock signal for data sampling for a buffer 150 such as an elasticity buffer, based on the clock signals CLK1-CLK8 and the clock selection signal CKSL supplied.
The buffer 150 consists of a multi-bit FIFO or of single bit flip-flops, or many bits, and is for absorbing deviation in the frequency that is arranged beforehand by the transmission and reception sides and clock jitter. Generally in serial communication, an asynchronous FIFO, the width of which is one bit, and depth ranges from several bits to dozens of bits is used. A synchronized data SDOUT is output from the buffer 150, which is read by a circuit of the next stage, and is processed as received data.
FIG. 12 shows a configuration of the input data edge detection unit 120. The input data edge detection unit 120 includes data flip-flops (hereinafter called flip-flop) 121a-121h corresponding to the eight clock signals CLK1-CLK8, respectively, each of which is in a phase different from the others, and exclusive OR (EXOR) gates 122a-122h, quantity of which is the same as the flip-flops 121a-121h. The flip-flops 121a-121h receive the corresponding clock signals CLK1-CLK8, respectively, and the serial data input signal SDIN. Further, each of output signals DFF1-DFF8 from the flip-flops 121a-121h, respectively, is supplied to two EXOR gates. For example, the output of flip-flop 121b is supplied to the EXOR gates 122a and 122b, the output of flip-flop 121c is supplied to the EXOR gates 122c and 122b, and a flip-flop 121h output is supplied to the EXOR gates 122h and 122a. 
Each of the EXOR gates 122a-122h outputs a signal (henceforth an edge signal) EDGE12, EDGE23, EDGE34, EDGE45, EDGE56, EDGE67, EDGE78, and EDGE89, respectively, which indicates edge position. An edge signal becomes “HIGH” when the data input signal SDIN changes at the timing of the phase difference of the two clock signals that are input. For example, the signal output from the EXOR gate 122a becomes “HIGH” when a data input signal changes at the timing of the phase difference of CLK1 and CLK2. The edge signals EDGE12-EDGE89 output from the EXOR gates 122a-122h are supplied to the clock judging unit 130 via independent routes.
Here, the number of clock signals having different phases is set at eight, however, the number may be different. Further, edge detection may be performed not by different phases but by a clock signal of a frequency higher than the transmission speed.
FIG. 13 is a timing chart of various signals related to the output timing of the clock signal WRCK for writing to buffer 150. As shown in FIG. 13, the first edge (rising edge) of the data input signal SDIN is located between the edge (rising edge) of the clock signal CLK1 and the edge (rising edge) of CLK2; the second edge (falling edge) of the data input signal SDIN is located between the edge (rising edge) of the clock signal CLK2 and the edge (rising edge) of CLK3; further, the third edge of the data input signal SDIN is located between the edge (rising edge) of the clock signal CLK3 and the edge (rising edge) of CLK4; and, furthermore, the last edge (falling edge) of the data input signal SDIN is located between the edge (rising edge) of the clock signal CLK2 and the edge (rising edge) of CLK3.
If an edge of the data input signal SDIN is detected, the detection pulse of a long period is output as a corresponding edge signal EDGE12-EDGE89. Based on the long detection pulse, CLK1 is output to EDGE12, the phase of CLK1 being about a half cycle late for sampling at the center of the input data. Similarly, CLK2 is output to EDGE23 as a synchronous timing signal, and CLK3 is further output to EDGE34. If there is no transition of edge in the synchronous timing signal and its cycle, the same clock as the previous cycle is output. Finally, the clock signal for writing WRCK to be output to the buffer 150 is generated.
Here, since the configuration after the input data edge detection unit 120, i.e., the operation of the timing of the clock judging unit 130, and the clock selection unit 140 shown in FIG. 12, are publicly known, an explanation thereabout is not presented.
Next, with reference to FIG. 14, a problem that may arise in the conventional bit synchronizing circuit 100 is explained. First, in order that the flip-flops 121a-121h operate normally, it is necessary to keep input data constant (setup hold) for a predetermined period before and after a clock. If the input data are not held to fixed values during the predetermined period, there is a possibility that output signals DFF1-DFF8 from the flip-flops 121a-121h become uncertain, i.e., neither 1 nor 0. This phenomenon is called “meta-stability”. At the place where mark A″ is shown in FIG. 14, the output signal DFF2 from the flip-flop 121b should be “HIGH”, however, the output signal DFF2 is in the meta-stable state, because the data input signal SDIN changes, and does not fill the setup hold timing requirement of the flip-flop 121b. Here, in FIG. 14, an example is shown where the level of the output signal DFF2, which is in the meta-stable state, shifts as the solid bold line indicates.
Further, at the place where mark B″ is given in FIG. 14, the output signal DFF6 from the flip-flop 121f should be “LOW”. However, the output signal DFF6 becomes “HIGH” in the case that the data input to the flip-flop 121f delay because of manufacturing problems such as the input resistance of the flip-flop 121f for the SDIN being extraordinarily high, there being cross talk in the signal line relative to the flip-flop 121f, and timing variation due to manufacturing of the semiconductor device.
When a fault occurs in the output signal of the flip-flops, such as shown by the places marked by A″ and B″, correct generation of the clock signal for writing to buffer WRCK 150 cannot be attained. Depending on the configuration of the circuit, the signal is not output at the original timing, and a timing error occurs at sampling by the buffer 150, resulting in, e.g., lack of WRCK that causes data dropping, and generation of plural WRCK signals in one cycle that causes retrieving too many bits. With reference to FIG. 14, errors of the synchronous timing signal and the clock signal WRCK occur at the places marked by C″ and D″, respectively. The errors cause erroneous reception of the serial data.
It is generally known that the meta-stability degrades the reliability of the bit synchronizing circuit, in addition to the problem of variations in the characteristics due to manufacturing, and a fault of a flip-flop used by the edge detection unit in the bit synchronizing circuit, etc. Since the meta-stability causes an erroneous operation, it is required that the meta-stability occurring be prevented, and a bit synchronizing circuit that is meta-stability proof be provided in order to raise the reliability of the circuit.
When a bit synchronizing circuit is built in a semiconductor device, testing of the device is performed by using an LSI tester, wherein a signal that is synchronous to a predetermined timing is input to the device, and a signal output from the device is measured and compared with an expected value. Then, if the output is similar to the expected value, the device passes the test. Otherwise, the device is considered a reject. However, in the case of a bit synchronizing circuit that operates serial data asynchronously at a high speed, a large number of asynchronous input patterns to a system clock have to be prepared on the LSI tester. Further, even if an acceptable device is tested by using the asynchronous input patterns, the receiving data sometimes differs from the expected value in cycles by the input of the asynchronous signal. Furthermore, the difference in data can be subject to variations in manufacturing the semiconductor device. For these reasons, debugging and completing a test program that is capable of accurately selecting acceptable devices from rejects takes a long time. Accordingly, a technology that copes with these problems is wanted.
Conventionally, the following bit synchronizing circuits are known. For example, JPL 7-193562 discloses a totally digital bit synchronizing circuit that is capable of handling high speed communications without using a counter. Although the patented circuit employs a general-purpose clock multilayer circuit or a D flip-flop, as does the present invention, the patented circuit uses only one edge detection unit, resulting in unreliable operations when the flip-flop in the bit synchronizing circuit meets a meta-stable state, which is a cause of faulty operations.
Further, JPL, 9-36849, A discloses a bit synchronizing circuit and a bit synchronous method that realize optimal sampling of input data, the duty rate of which fluctuates, by detecting a rising edge and a falling edge of a signal from a data sampling unit, which is a component of the bit synchronizing circuit, and is for sampling an incoming signal and arranging the sampled signal into an n series of signals, another component thereof being a selection output unit for selecting a signal that is synchronized with a received burst signal out of the sampled n series of the signals. However, since this bit synchronous method uses both edges where a data value changes, there is a problem that the sampling cannot be performed at a high speed. Further, since only one circuit is used for detecting the edges, when the flip-flop of the bit synchronizing circuit comes to a meta-stable state, faulty operations occur, producing a problem of degraded reliability.
Furthermore, JPL, 10-247903, A discloses a bit synchronizing circuit that complies with a high-speed burst signal that is sporadically generated, input timing of which is uncertain, and complies with phase fluctuation without using a high-speed clock that exceeds receiving data speed. However, this circuit uses only one phase comparison circuit, and therefore, lacks reliability.